Semiconductor component

ABSTRACT

A semiconductor component having electrode terminals  14  formed in rectangular planar shapes arranged in parallel on an electrode forming surface of a semiconductor chip and formed with rerouting patterns  16  electrically connected with the electrode terminals  14  through vias on the surface of an electrical insulating layer covering the electrode forming surface, characterized in that the planar arrangement of the via pads  20  formed on the surface of the electrical insulating layer is made an arrangement alternately offset to one side and the other side of the longitudinal direction of the electrode terminals  14  and in that rerouting patterns  16  are provided connected to the via pads  20 . The present invention enables easy formation of rerouting patterns even when the electrode terminals are arranged at fine intervals.

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor componentcharacterized by the provision of rerouting patterns at a semiconductorchip where electrode terminals are arranged at fine intervals.

BACKGROUND ART

[0002] Wafer level packages are semiconductor components obtained byprocessing the surface of a wafer at the semiconductor wafer stage toform rerouting patterns. After performing predetermined processing atthe wafer level, they are divided into the individual pieces. Thesesemiconductor components are then either mounted on mother boards orstacked in a chip-on-chip configuration.

[0003] When producing such semiconductor components, the individualchips formed on the semiconductor wafer are formed with interconnects(called “rerouting”) from their electrode terminals to predeterminedpositions where external electrodes are formed or else the interconnectsare connected by wire bonding for mounting on a mother board etc.

[0004]FIG. 6 is a view of the state where the surface of a semiconductorwafer 10 is provided with an electrical insulating layer 12 and thesurface of the insulating layer 12 is formed with a rerouting pattern 16electrically connected to an electrode terminal 14 through a via 15. Thererouting pattern is for example electrically connected at one end withthe electrode terminal 14 and formed at the other end with a landportion for bonding with an external connection terminal or a bondingportion for wire bonding. Rerouting patterns 16 can be formed into anypattern on the surface of the insulating layer 12, so the reroutingpatterns 16 are suitably led out from the electrode terminals 14 toarrange land portions or bonding portions.

[0005]FIG. 5 shows an example of conventional formation of reroutingpatterns. It shows a plan arrangement of connecting portions betweenelectrode terminals 14 and rerouting patterns 16. The electrodeterminals 14 are formed in square shapes at constant intervals on thesurface of the semiconductor wafer 10. Via holes 18 are formed in theplane of the electrode terminals 14, while conductor layers at theinside of the via holes 18 are formed as vias. Via pads 20 are formedwith certain widths at the peripheral rims of the via holes 18. Theseare to ensure the electrical connection between the rerouting patterns16 and the vias.

[0006] Recent semiconductor chips, however, are becoming smaller in sizeand increased in number of terminals, so the problem has been arisingthat the interval of arrangement between the electrode terminals 14 hasbecome narrower and sufficient space S between adjoining via pads 20 canno longer be obtained. In the example shown in FIG. 5, the diameterdimension R of the via pads 20 is set larger than the width dimension ofthe electrode terminals 14, but when the interval of arrangement betweenelectrode terminals 14 becomes narrower, it is possible to secure theinterval of arrangement between via pads 20 by making the via holes 18smaller and reducing the diameter dimension R of the via pads 20.Forming the via holes 18 smaller, however, gives rise to problems in theprocessing accuracy and the problem of a higher contact resistance.Further, if the via pads 20 are made smaller, there is the problem thatthe reliability of the electrical connection with the rerouting patterns16 becomes lower.

[0007] Further, when providing bonding portions at the reroutingpatterns and connecting with a mother board or other semiconductor chipby wire bonding, it becomes necessary to provide the bonding portionsnear the electrode terminals of the semiconductor chip. In this case,there is the problem that it is difficult to secure sufficient bondingportions near the electrode terminals when the interval of arrangementof the electrode terminals of the semiconductor chip is narrow.

DISCLOSURE OF THE INVENTION

[0008] The object of the present invention is to provide a semiconductorcomponent enabling the easy and reliable formation of rerouting patternswithout reducing the diameter of the via pads or narrowing of thererouting widths even when electrode terminals are arranged at fineintervals, enabling bonding portions to be secured near the electrodeterminals, and enabling connection by wire bonding to be easily handled.

[0009] To achieve the above object, the present invention is configuredas follows:

[0010] That is, there is provided a semiconductor component havingelectrode terminals formed in rectangular planar shapes arranged inparallel on an electrode forming surface of a semiconductor chip andformed with rerouting patterns electrically connected with saidelectrode terminals through vias on the surface of an electricalinsulating layer covering the electrode forming surface, characterizedin that the planar arrangement of the via pads formed on the surface ofthe electrical insulating layer is made an arrangement alternatelyoffset to one side and the other side of the longitudinal direction ofthe electrode terminals and in that the rerouting patterns are providedconnected to the via pads.

[0011] Further, the component is characterized in that bonding portionsobtained by forming the rerouting patterns wider and to be connected bywire bonding are provided at portions near via pads of said reroutingpatterns.

[0012] Further, the component is characterized in that said bondingportions are provided by being led out from the via pads on to regionsof the adjoining electrode terminals.

[0013] Further, there is provided a semiconductor component formed onthe surface of an electrical insulating layer covering an electrodeterminal forming surface of a semiconductor chip with rerouting patternselectrically connected with electrode terminals through vias,characterized in that bonding portions obtained by forming the reroutingpatterns wider and to be connected by wire bonding are provided atportions near via pads of said rerouting patterns.

[0014] Further, the component is characterized in that said bondingportions are provided at positions not interfering with each other atportions near said via pads.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 shows the planar arrangement of via pads and electrodeterminals formed on rerouting patterns.

[0016]FIG. 2 shows the planar arrangement of rerouting patterns andbonding portions.

[0017]FIGS. 3A and 3B show other examples of the planar arrangement ofrerouting patterns and bonding portions.

[0018]FIG. 4 shows an example of mounting a semiconductor chip formedwith rerouting patterns.

[0019]FIG. 5 shows the planar arrangement of electrode terminals andrerouting patterns of the prior art.

[0020]FIG. 6 is a sectional view of the configuration of a reroutingpattern.

BEST MODE FOR WORKING THE INVENTION

[0021] Next, preferred embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

[0022]FIG. 1 is an explanatory view of an example of formation ofrerouting patterns in a semiconductor component according to the presentinvention. In the figure, 14 shows electrode terminals formed on awafer, while 16 shows rerouting patterns electrically connected to theelectrode terminals 14. The characterizing feature in the semiconductorcomponent of the present embodiment is that via pads 20 arrangedelectrically connected to the electrode terminals 14 formed inrectangular planar shapes and arranged in parallel are arranged offsetto one side and the other side in the longitudinal direction of theelectrode terminals 14.

[0023] If the semiconductor chip is made smaller and the interval ofarrangement of the electrode terminals 14 becomes narrower, the bondingareas of the electrode terminals become smaller, so the electrodeterminals 14 are formed into long, narrow rectangular shapes to securethe bonding areas. In the semiconductor component of the presentembodiment, provision is made of a semiconductor chip formed withelectrode terminals 14 formed into such rectangular shapes characterizedin that the via pads 20 are arranged in a zig-zag form so as to securethe space between adjoining via pads 20 and enable rerouting withoutreducing the diameter of the via pads 20 or reducing the widthdimensions of the rerouting patterns 16 even when the interval ofarrangement between electrode terminals 14 becomes narrower.

[0024] Note that the method of forming rerouting patterns 16electrically connected to the electrode terminals 14 is similar to theconventional method of forming rerouting patterns 16 shown in FIG. 6.That is, an electrical insulating layer 12 is formed on the surface of asemiconductor wafer 10, then via holes 18 are formed matched with thepositions of arrangement of the electrode terminals 14 and the insidewalls of the via holes 18 and the surface of the insulating layer 12 areplated to form a conductor layer and form rerouting patterns 16. In thepresent embodiment, since the via pads 20 are arranged in a zig-zagconfiguration, when forming via holes 18 in the insulating layer 12, thevia holes 18 are formed alternately at positions offset to one side andthe other side of the longitudinal direction of the electrode terminals14.

[0025] After forming the via holes 18, the inside walls of the via holes18 and the surface of the insulating layer 12 are formed with a platingseed layer by sputtering. Next, the surface of the plating seed layer iscovered by a photosensitive resist, then the photosensitive resist isexposed and developed to form a resist pattern exposing the portions forforming the rerouting patterns 16 and via pads 20. Next, copper iselectrolytically plated using the plating seed layer as a plating powerlayer to form conductor layers at the exposed portions of the platingseed layer, then the resist pattern is dissolved and removed, and theexposed portions of the plating seed layer are etched away to formrerouting patterns 16 electrically connected to the electrode terminals14 by the vias.

[0026] Note that the procedure for forming the rerouting patterns 16 isperformed for the entire electrode forming surface of the semiconductorwafer. An actual semiconductor wafer is formed with a large number ofindividual semiconductor chips arranged connected in the vertical andhorizontal directions, so rerouting patterns 16 are formed in apredetermined pattern corresponding to the arrangement of thesesemiconductor chips.

[0027] Further, after forming the rerouting patterns 16, thesemiconductor wafer can be divided into the individual pieces so as toobtain the individual semiconductor chips formed with the reroutingpatterns 16.

[0028] Normally, the diameter of the via pads 20 becomes larger than thewidth of the rerouting patterns 16. Therefore, as shown in FIG. 1, ifarranging the positions for arrangement of the via pads 20 in the planarregions where the electrode terminals 14 are formed alternately offsetto one side and the other side for each electrode terminal, thearrangement where the via pads 20 formed at adjoining electrodeterminals 14 overlap each other can be eliminated and extra space can besecured between adjoining via pads 20. Therefore, it is possible tosecure sufficient space between the via pads 20 and rerouting patterns16 even if the via pads 20 and the rerouting patterns 16 are arrangedadjoining each other. Due to this, even when the interval of arrangementof the electrode terminals 14 becomes narrower, it becomes possible toeasily form the rerouting patterns 16 without reducing the diameterdimension of the via pads 20.

[0029] With a conventional method of forming rerouting patterns, if thewidth dimension of the electrode terminals 14 is 80 μm and the intervalof arrangement between electrode terminals 14 is 10 μm, that is, thepitch of the electrode terminals 14 is 90 μm, if the diameter of the viapads is made 80 μm and the width of the rerouting patterns is made 50μm, the interval between via pads becomes 10 μm, but according to themethod of the present invention, it is possible to secure an interval of25 μm as the interval between the via pads and adjoining reroutingpatterns (S1 in FIG. 1).

[0030] Note that in the embodiment shown in FIG. 1, the reroutingpatterns 16 are led out straight from the electrode terminals 14, but byarranging the via pads 20 offset in the planar regions of the electrodeterminals 14, as shown in FIG. 2, it is possible to form bondingportions for wire bonding at the rerouting patterns 16.

[0031] The arrangement of the rerouting patterns 16 shown in FIG. 2 ischaracterized by, for the via pad 20 a arranged at one side of theelectrode terminal (front end side), forming the rerouting pattern 16 byleading it out from the via pad 20 a and forming the bonding portion 22a by extending it directly from the via pad 20 a at the space portionabove the adjoining electrode terminal 14 from the via pad 20 a and by,for the via pad 20 b arranged at the other side of the electrodeterminal 14 (rear end side), forming the broad bonding portion 22 bdirectly from the via pad 20 b at the pattern led out from the via pad20 b.

[0032] The bonding portions 22 a and 22 b formed at the reroutingpatterns 16 become the portions bonded by bonding wires whenelectrically connecting the rerouting patterns 16 with anothersemiconductor chip or a mother board (package) by wire bonding. FIG. 2shows an example of connecting the electrode terminals 30 of anothersemiconductor chip or mother board (package) with the bonding portions22 a and 22 b by bonding wires 32.

[0033] If arranging the via pads in the planar regions of the electrodeterminals 14 offset to one side and the other side as in thisembodiment, it is possible to effectively use the surface space of theinsulating layer 12 to form the bonding portions 22 a and 22 b.

[0034] Note that according to the present invention, the method offorming the bonding portions used for connection of the reroutingpatterns by wire bonding can also be applied to the case of arrangingthe via pads serially in the same way as in the past. FIGS. 3A and 3Bshow cases of forming bonding portions 22 at rerouting patterns 16 inthe case of the conventional arrangement of via pads. In FIG. 3A, forone via pad 20 a, the broad bonding portion 22 a is extended directlyfrom the via pad 20 a at the rear end side and the narrow reroutingpattern 16 is led out from the bonding portion 22 a, while for the othervia pad 20 b, the bonding portion 22 b is extended toward the facingrerouting pattern 16 at a position not interfering with the bondingportion 22 a and a narrow rerouting pattern 16 is led out from thebonding portion 22 b.

[0035] Further, in the embodiment shown in FIG. 3B, for the via pad 20a, the bonding portion 22 a is formed extending from the side edge ofthe rerouting pattern toward the facing via pad 20 b at a position nearthe via pad 20 a, while for the via pad 20 b, the bonding portion 22 bis formed extending from the rerouting pattern led out from the via pad20 toward the facing rerouting pattern at a position where interferencewith the bonding portion 22 b does not occur.

[0036] The embodiments shown in FIGS. 3A and 3B form the portions nearthe via pads 20 a and 20 b broadly to form the bonding pads 22 a and 22b. In particular, by selecting positions where the bonding portions 22 aand 22 b do not interfere near the via pads 20 a and 20 b, it ispossible to secure the required bonding regions and reliably wire bondthe rerouting patterns.

[0037]FIG. 4 shows an example of mounting a semiconductor component 40formed with rerouting patterns 16 having bonding portions 22 a and 22 bshown in FIG. 2. In this example, another semiconductor chip 42 ismounted on the semiconductor component 40 and the semiconductorcomponent 40 is mounted on a mother board 44. The semiconductor chip 42is electrically connected by flip-chip connection to the land portions16 b of the rerouting patterns 16 of the semiconductor component 40through bumps 42 a, while the semiconductor component 40 is electricallyconnected by wire bonding to the mother board 44.

[0038] Note that instead of the mother board 44, it is also possible tomount the semiconductor component 40 on another semiconductor chip.Further, instead of the mother board 44, it is possible to mount thesemiconductor component 40 on another semiconductor package.

[0039] By providing the bonding portions 22 a and 22 b at the reroutingpatterns 16 in this way, it is possible to electrically connect thesemiconductor component with another semiconductor chip or a motherboard or semiconductor package by wire bonding and possible to providevarious types of electronic devices.

[0040] Note that the bonding portions formed near the via pads can beformed into a suitable pattern in accordance with the arrangement of thevia pads and rerouting patterns. The arrangement of the reroutingpatterns and bonding portions are not limited to the above embodiments.

INDUSTRIAL APPLICABILITY

[0041] According to the semiconductor component of the presentinvention, as explained above, it becomes possible to give a zig-zagplanar arrangement of the via pads connected to the electrode terminalsand effectively secure space for arranging the via pads and reroutingpatterns and it becomes possible to easily form rerouting patterns evenwhen electrode terminals are arranged at fine intervals. Further, byforming broad portions at the rerouting patterns to provide bondingportions, the remarkable effect is exhibited that it becomes possible touse them as portions for electrically connecting the rerouting patternsby wire bonding.

1. A semiconductor component having electrode terminals formed inrectangular planar shapes arranged in parallel on an electrode formingsurface of a semiconductor chip and formed with rerouting patternselectrically connected with said electrode terminals through vias on thesurface of an electrical insulating layer covering the electrode formingsurface, said semiconductor component characterized in that the planararrangement of the via pads formed on the surface of the electricalinsulating layer is made an arrangement alternately offset to one sideand the other side of the longitudinal direction of the electrodeterminals and in that the rerouting patterns are provided connected tothe via pads.
 2. A semiconductor component as set forth in claim 1,characterized in that bonding portions obtained by forming the reroutingpatterns wider and to be connected by wire bonding are provided atportions near via pads of said rerouting patterns.
 3. A semiconductorcomponent as set forth in claim 2, characterized in that said bondingportions are provided by being led out from the via pads on to regionsof the adjoining electrode terminals.
 4. A semiconductor componentformed on the surface of an electrical insulating layer covering anelectrode terminal forming surface of a semiconductor chip withrerouting patterns electrically connected with electrode terminalsthrough vias, said semiconductor component characterized in that bondingportions obtained by forming the rerouting patterns wider and to beconnected by wire bonding are provided at portions near via pads of saidrerouting patterns.
 5. A semiconductor component as set forth in claim4, characterized in that said bonding portions are provided at positionsnot interfering with each other at portions near said via pads.
 6. Asemiconductor component as set forth in claim 1, characterized in thatanother semiconductor chip is mounted to said semiconductor chip.
 7. Asemiconductor package characterized in that the semiconductor componentset forth in claim 6 is mounted on any one of a mother board, anothersemiconductor chip, or another semiconductor package.
 8. A semiconductorcomponent as set forth in claim 2, characterized in that anothersemiconductor chip is mounted to said semiconductor chip.
 9. Asemiconductor component as set forth in claim 3, characterized in thatanother semiconductor chip is mounted to said semiconductor chip.
 10. Asemiconductor component as set forth in claim 4, characterized in thatanother semiconductor chip is mounted to said semiconductor chip.
 11. Asemiconductor component as set forth in claim 5, characterized in thatanother semiconductor chip is mounted to said semiconductor chip.